Parasitic effects in multi-gate MOSFETs

Kobayashi, Yusuke ; Raghunathan Manoj, C. ; Tsutsui, Kazuo ; Hariharan, Venkanarayan ; Kakushima, Kuniyuki ; Ramgopal Rao, V. ; Ahmet, Parhat ; Iwai, Hiroshi (2007) Parasitic effects in multi-gate MOSFETs IEICE - Transactions on Communications, E90-C (10). pp. 2051-2056. ISSN 0916-8516

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In this paper, we have systematically investigated parasitic effects due to the gate and source-drain engineering in multi-gate transistors. The potential impact of high-K dielectrics on multi-gate MOSFETs (MuGFETs), such as FinFET, is evaluated through 2D and 3D device simulations over a wide range of proposed dielectric values. It is observed that introduction of high-K dielectrics will significantly degrade the short channel effects (SCEs), however a combination of oxide and high-K stack can effectively control this degradation. The degradation is mainly due to the increase in the internal fringe capacitance coupled with the decrease in gate-channel capacitance. From the circuit perspective, an optimum K value has been identified through mixed mode simulations. Further, as a part of this work, the importance of optimization of the shape of the spacer region is highlighted through full 3D simulations.

Item Type:Article
Source:Copyright of this article belongs to Oxford University Press.
Keywords:Multi-gate; Fin-FETs; High-K Dielectric; Fringe Capacitance; Parasitic Effect
ID Code:44471
Deposited On:22 Jun 2011 05:29
Last Modified:22 Jun 2011 05:29

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