Gate stack architecture analysis and channel engineering in deep sub-micron MOSFETs

Abstract

Scaling of metal-oxide-semiconductor (MOS) transistors to smaller dimensions has been a key driving force in the IC industry. As we approach the sub-quarter micron regime, a whole new set of problems regarding the device performance arises. One of the major concerns is the high gate leakage current. To address this problem, a lot of effort has been concentrated on the use of the so-called "high-K dielectrics" as gate insulators. However, the implications of using these materials on the electrical performance of MOS devices need to be studied. This work is an effort towards the same. There has also been a lot of discussion about the trade-offs related to the use of retrograde channel profiles in deep sub-micron transistors. It is also shown in this work that a retrograde profile can be optimized to have an advantage over uniform doping.