Optimization and realization of sub-100-nm channel length single halo p-MOSFETs

Borse, D. G. ; M. Rani, K. N. ; Jha, N. K. ; Chandorkar, A. N. ; Vasi, J. ; Ramgopal Rao, V. ; Cheng, B. ; Woo, J. C. S. (2002) Optimization and realization of sub-100-nm channel length single halo p-MOSFETs IEEE Transactions on Electron Devices, 49 (6). pp. 1077-1079. ISSN 0018-9383

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Official URL: http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arn...

Related URL: http://dx.doi.org/10.1109/TED.2002.1003752

Abstract

Single halo p-MOSFETs with channel lengths down to 100 nm are optimized, fabricated, and characterized as part of this study. We show extensive device characterization results to study the effect of large angle VT adjust implant parameters on device performance and hot carrier reliability. Results on both conventionally doped and single halo p-MOSFETs have been presented for comparison purposes.

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ID Code:44441
Deposited On:22 Jun 2011 03:50
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