Siva Ram Murthy, C. ; Rajaraman, V. (1987) A multi-microprocessor architecture for solving partial differential equations Microprocessing & Microprogramming, 20 (1-3). pp. 113-117. ISSN 0165-6074
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Official URL: http://linkinghub.elsevier.com/retrieve/pii/016560...
Related URL: http://dx.doi.org/10.1016/0165-6074(87)90128-1
Abstract
This paper presents the architecture of a fault-tolerant, special-purpose multi-microprocessor system for solving Partial Differential Equations (PDEs). The modular nature of the architecture allows the use of hundreds of Processing Elements (PEs) for high throughput. Its performance is evaluated by both analytical and simulation methods. The results indicate that the system can achieve high operation rates and is not sensitive to inter-processor communication delay.
| Item Type: | Article |
|---|---|
| Source: | Copyright of this article belongs to Elsevier Science. |
| ID Code: | 38359 |
| Deposited On: | 29 Apr 2011 08:05 |
| Last Modified: | 29 Apr 2011 08:40 |
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