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DimensionsBanerjee, S. ; Mukhopadhyay, D. ; Rao, C.V.G. ; Chowdhury, D.R. (2006) An integrated DFT solution for mixed-signal SOCs IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25 (7). pp. 1368-1377. ISSN 0278-0070
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Official URL: https://doi.org/10.1109/TCAD.2005.855972
Related URL: http://dx.doi.org/10.1109/TCAD.2005.855972
Abstract
This paper introduces an efficient implementation of a test access mechanism (TAM) for mixed-signal system-on-chip (MSOC) testing. The design-for-testability (DFT) strategy has been developed to make the testing of analog cores digitally compliant. The mixed-signal cores have been accessed through specially design mechanisms (switches). A computer-aided test (CAT) tool employing the proposed algorithm has been developed. Extensive experiments have been performed on MSOC benchmarks built of ISCAS'89 circuits for digital cores and ITC'97 circuits for analog cores. Results show that the CAT tool provides a hardware-efficient integrated solution.
| Item Type: | Article |
|---|---|
| Source: | Copyright of this article belongs to IEEE. |
| Keywords: | Dft for Socs; Mixed-signal Test; Test of System on Chip; Test Scheduling; Vlsi Testing |
| ID Code: | 142864 |
| Deposited On: | 25 Jun 2026 11:43 |
| Last Modified: | 25 Jun 2026 11:43 |
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