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DimensionsMukhopadhyay, Debdeep ; Sengar, Gaurav ; Chowdhury, Dipanwita Roy (2007) Hierarchical Verification of Galois Field Circuits IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 26 (10). pp. 1893-1898. ISSN 0278-0070
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Official URL: https://doi.org/10.1109/TCAD.2007.895755
Related URL: http://dx.doi.org/10.1109/TCAD.2007.895755
Abstract
This paper proposes a hierarchical method for the formal hardware verification of Galois field architecture circuits. The reduced ordered functional decision diagram has been explored. The proposed method has been found to lead to significant gains in time and space, depending on the resources that are available. The theoretical claims that were made have been supported by experiments.
| Item Type: | Article |
|---|---|
| Source: | Copyright of this article belongs to IEEE. |
| Keywords: | Composite Field; Formal Verification; Functional Decision Diagrams (Dds); Galois Fields; Hierarchical; Multipliers |
| ID Code: | 142798 |
| Deposited On: | 24 Jun 2026 07:20 |
| Last Modified: | 24 Jun 2026 07:20 |
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