Johnson, Anju P. ; Chakraborty, Rajat Subhra ; Mukhopadhyay, Debdeep (2015) A PUF-Enabled Secure Architecture for FPGA-Based IoT Applications IEEE Transactions on Multi-Scale Computing Systems, 1 (2). pp. 110-122. ISSN 2332-7766
Full text not available from this repository.
Official URL: https://doi.org/10.1109/TMSCS.2015.2494014
Related URL: http://dx.doi.org/10.1109/TMSCS.2015.2494014
Abstract
The Internet of Things (IoT) is a dynamic, ever-evolving “living” entity. Hence, modern Field Programmable Gate Array (FPGA) devices with Dynamic Partial Reconfiguration (DPR) capabilities, which allow in-field non-invasive modifications to the circuit implemented on the FPGA, are an ideal fit. Usually, the activation of DPR capabilities requires the procurement of additional licenses from the FPGA vendor. In this work, we describe how IoTs can take advantage of the DPR capabilities of FPGAs, using a modified DPR methodology that does not require any paid “add-on” utility, to implement a lightweight cryptographic security protocol. We analyze possible threats that can emanate from the availability of DPR at IoT nodes, and propose possible solution techniques based on Physically Unclonable Function (PUF) circuits to prevent such threats.
| Item Type: | Article |
|---|---|
| Source: | Copyright of this article belongs to IEEE. |
| Keywords: | Cryptographic Protocol; Dynamic Partial Reconfiguration; Internet of Things; Field Programmable Gate Arrays; Hardware Trojans; Physically Unclonable Functions |
| ID Code: | 142755 |
| Deposited On: | 23 Jun 2026 09:22 |
| Last Modified: | 23 Jun 2026 09:22 |
Repository Staff Only: item control page

Dimensions
Dimensions