Sengar, Gaurav ; Mukhopadhyay, Debdeep ; Chowdhury, Dipanwita Roy (2007) Secured Flipped Scan-Chain Model for Crypto-Architecture IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 26 (11). pp. 2080-2084. ISSN 0278-0070
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Official URL: https://doi.org/10.1109/TCAD.2007.906483
Related URL: http://dx.doi.org/10.1109/TCAD.2007.906483
Abstract
Scan chains are exploited to develop attacks on cryptographic hardware and steal intellectual properties from the chip. This paper proposes a secured strategy to test designs by inserting a certain number of inverters between randomly selected scan cells. The security of the scheme has been analyzed. Two detailed case studies of RC4 stream cipher and AES block cipher have been presented to show that the proposed strategy prevents existing scan-based attacks in the literature. The elegance of the scheme lies in its less hardware overhead.
| Item Type: | Article |
|---|---|
| Source: | Copyright of this article belongs to IEEE. |
| Keywords: | Block Ciphers; Design_For_Testability; Hardware Overhead; Scan_Based_Test; Scan-Chain-Based Attacks; Security Margin; Stream Ciphers |
| ID Code: | 142752 |
| Deposited On: | 23 Jun 2026 08:46 |
| Last Modified: | 23 Jun 2026 09:13 |
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