Thilakam, Krishna ; Jhunjhunwala, Ashok (1989) Proposed high speed packet switch for broadband integrated networks Computer Communications, 12 (6). pp. 337-348. ISSN 0140-3664
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Official URL: http://linkinghub.elsevier.com/retrieve/pii/014036...
Related URL: http://dx.doi.org/10.1016/0140-3664(89)90004-2
Abstract
The design of a high speed, broadband packet switch with two priority levels for application in integrated voice/data networks is presented. The packet switch can efficiently cope with 128 byte packets converging on it from eight 140 Mbit/s dynamic time division multiplexed fibre optic links. The packet switch throughput varies with the load and traffic composition, and the delay experienced by voice and data packets is within 300 μs and 3 ms, respectively. The design is implemented by task-sharing in a multi-processor configuration. The design of the packet switch, including its subsystems, is detailed here.
| Item Type: | Article |
|---|---|
| Source: | Copyright of this article belongs to Elsevier Science. |
| Keywords: | Broadband Integrated Services Digital Networks; High Speed Packet Switch; Voice/Data Integration; Backbone Network |
| ID Code: | 14043 |
| Deposited On: | 12 Nov 2010 09:16 |
| Last Modified: | 17 Feb 2011 09:51 |
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