On synthesis of easily testable (k, K) circuits

Naidu, S.R. ; Vijay Chandru, (2003) On synthesis of easily testable (k, K) circuits IEEE Transactions on Computers, 52 (11). pp. 1490-1494. ISSN 0018-9340

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Official URL: http://doi.org/10.1109/TC.2003.1244946

Related URL: http://dx.doi.org/10.1109/TC.2003.1244946

Abstract

A (k, K) circuit is one which can be decomposed into nonintersecting blocks of gates where each block has no more than K external inputs, such that the graph formed by letting each block be a node and inserting edges between blocks if they share a signal line, is a partial k-tree. (k, K) circuits are special in that they have been shown to be testable in time polynomial in the number of gates in the circuit, and are useful if the constants k and K are small. We demonstrate a procedure to synthesise (k, K) circuits from a special class of Boolean expressions.

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Deposited On:20 Dec 2022 05:31
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