Mohapatra, N. R. ; Nair, D. R. ; Mahapatra, S. ; Rao, V. R. ; Shukuri, S. (2003) The impact of channel engineering on the performance reliability and scaling of CHISEL NOR flash EEPROMs In: 2003 33rd Conference on European Solid-State Device Research, ESSDERC '03, 16-18 Sept, 2003, Estoril, Portugal.
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Official URL: http://ieeexplore.ieee.org/document/1256933/
Related URL: http://dx.doi.org/10.1109/ESSDERC.2003.1256933
Abstract
The programming performance, cycling endurance and scaling of CHISEL NOR flash EEPROMs is studied for two different (halo and no-halo) channel engineering schemes. Programming speed under identical bias, bias requirements under similar programming time, cycling endurance and drain disturb are compared. The scaling properties of programming time (at a fixed bias), bias (at a fixed programming time) and program/disturb margin are studied as cell floating gate length is scaled. The relative merits of these channel engineering schemes are discussed from the viewpoint of futuristic CHISEL cell design.
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Source: | Copyright of this article belongs to Institute of Electrical and Electronics Engineers. |
| ID Code: | 112701 |
| Deposited On: | 12 Apr 2018 07:22 |
| Last Modified: | 12 Apr 2018 07:22 |
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