Using Soft Secondary Electron Programming to reduce drain disturb in floating-gate NOR flash EEPROMs

Abstract

A novel concept of Soft Secondary Electron Programming (SSEP) is introduced and shown to be a promising programming scheme for scaled NOR flash electrically erasable programmable read-only memories. Although the mechanism is similar to that of the Channel-initiated Secondary Electron (CHISEL) programming, SSEP uses an "optimum" substrate bias that results in a lower drain disturb compared with both Channel Hot Electron (CHE) and conventional CHISEL programming schemes. The concept behind minimizing drain disturb is discussed. SSEP is shown to give faster programming and lower disturb than CHE at all operating conditions, as well as better program/disturb margin compared with conventional CHISEL programming at similar program speed or disturb time. The effect of repeated program/erase cycling using SSEP is compared against CHE and CHISEL cycling.