Datta, A. ; Bharath Kumar, P. ; Mahapatra, S. (2007) Dual-bit/cell SONOS flash EEPROMs: Impact of channel engineering on programming speed and bit coupling effect IEEE Electron Device Letters, 28 (5). pp. 446-448. ISSN 0741-3106
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Official URL: http://ieeexplore.ieee.org/document/4160016/
Related URL: http://dx.doi.org/10.1109/LED.2007.895406
Abstract
Programming performance of dual-bit silicon-oxide-nitride-oxide-silicon memories is studied on cells fabricated using different channel engineering schemes. Both halo and compensation implants are shown to impact the programming speed, bit coupling and read disturb, and can be suitably adjusted to optimize the cell operation. The doping dependence of bit coupling and the programming speed are verified using well-calibrated 2-D device simulations.
| Item Type: | Article |
|---|---|
| Source: | Copyright of this article belongs to Institute of Electrical and Electronics Engineers. |
| Keywords: | 2-bit Operation; Bit Coupling; Compensation Implant; Flash; Halo Implant; Localized Charge Storage; Non Volatile Semiconductor Memory (NVSM); Program Speed; Read Disturb; SONOS |
| ID Code: | 112652 |
| Deposited On: | 02 Apr 2018 09:32 |
| Last Modified: | 02 Apr 2018 09:32 |
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