Sandhya, C. ; Ganguly, U. ; Singh, K. K. ; Singh, P. K. ; Olsen, C. ; Seutter, S. M. ; Hung, R. ; Conti, G. ; Ahmed, K. ; Krishna, N. ; Vasi, J. ; Mahapatra, S. (2008) Nitride engineering and the effect of interfaces on Charge Trap Flash performance and reliability In: 2008 IEEE International Reliability Physics Symposium, IRPS 2008, 27 April-1 May, 2008, Phoenix, AZ, USA.
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Official URL: http://ieeexplore.ieee.org/document/4558919/
Related URL: http://dx.doi.org/10.1109/RELPHY.2008.4558919
Abstract
The performance and reliability of Charge Trap Flash with single and bi-layer Si-rich and N-rich nitride as the storage node is studied. Single layer devices show lower memory window and poor cycling endurance and the underlying physical mechanisms for these issues are explained. An engineered trap layer consisting of Si-rich and N-rich nitride interfaced by a SiON barrier layer is proposed. The effect of varying the SiON interfacial layer position on memory window and reliability is investigated. Optimum bi-layer device shows higher memory window and negligible degradation due to cycling (at higher memory window) compared to single layer films. The role of SiON interface in improving the performance and reliability of bi-layer stacks is explained.
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Source: | Copyright of this article belongs to Institute of Electrical and Electronics Engineers. |
| Keywords: | Data Retention; SONOS Eeproms; Charge Trap Flash; Bandgap Engineering; Endurance |
| ID Code: | 112630 |
| Deposited On: | 12 Apr 2018 07:22 |
| Last Modified: | 12 Apr 2018 07:22 |
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