Singh, Pawan ; Sandhya, C. ; Auluck, Kshitij ; Bisht, Gaurav ; Sivatheja, M. ; Mukhopadhyay, Gautam ; Mahapatra, Souvik ; Hofmann, Ralf (2010) Applicability of dual layer metal nanocrystal flash memory for NAND 2 or 3-bit/cell operation: Understanding the anomalous breakdown and optimization of P/E conditions In: 2010 IEEE International Conference on Reliability Physics Symposium (IRPS), 2-6 May, 2010, Anaheim, CA, USA.
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Official URL: http://ieeexplore.ieee.org/document/5488690/
Related URL: http://dx.doi.org/10.1109/IRPS.2010.5488690
Abstract
Large memory window (6–9 V) Program/Erase (P/E) cycling endurance is studied for evaluating their suitability for MLC operation. Effect of NC area coverage and device size is evaluated using statistical method. Constant Voltage Stress (CVS) measurements and 2-D simulations are extensively used to evaluate the impact of carrier; type, fluence and energy on the defect generation process in the gate stack. Degradation during P and E are isolated to allow individual optimization for improving the cycling reliability. P/E cycling endurance ≫104 at 8V MW and ≫2.5 × 103 at 9 V MW are shown for first time in metal NC memory devices using the proposed distributed cycling scheme.
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Source: | Copyright of this article belongs to Institute of Electrical and Electronics Engineers. |
| Keywords: | Reliability; Component; Metal Nanocrystal; Flash Memory; MLC |
| ID Code: | 112617 |
| Deposited On: | 12 Apr 2018 07:22 |
| Last Modified: | 12 Apr 2018 07:22 |
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