Goel, N. ; Dubey, P. ; Kawa, J. ; Mahapatra, S. (2015) Impact of time-zero and NBTI variability on sub-20 nm FinFET based SRAM at low voltages In: 2015 IEEE International Conference on Reliability Physics Symposium (IRPS), 19-23 April 2015, Monterey, CA, USA.
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Official URL: http://ieeexplore.ieee.org/document/7112783/
Related URL: http://dx.doi.org/10.1109/IRPS.2015.7112783
Abstract
BSIM-CMG based HSPICE framework is developed for simulating time-zero and Negative Bias Temperature Instability (NBTI) variability of SRAM performance parameters. Time-zero variability of Read Static Noise Margin, Hold Static Noise Margin and Flip-Time for different process corners are simulated. Models used for SPICE simulation are foundry qualified sub-20 nm FinFET for two types of 6T SRAM cells, High-Speed and High-Density cells. The Impact of stochastic BTI for DC and AC activity stress on these parameters are studied for relevant worst-case process corner. The impact of Vdd reduction on time-zero and post-BTI SRAM parameter variability is also studied. Critical failure situations are identified.
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Source: | Copyright of this article belongs to Institute of Electrical and Electronics Engineers. |
| Keywords: | HSPICE; NBTI; Finfet; Variability; SRAM; SNM; Flip-time; Reaction-diffusion Model; BSIM-CMG |
| ID Code: | 112570 |
| Deposited On: | 11 Apr 2018 11:08 |
| Last Modified: | 11 Apr 2018 11:08 |
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