Predictive TCAD for NBTI stress-recovery in various device architectures and channel materials

Mishra, Subrat ; Wong, Hiu Yung ; Tiwari, Ravi ; Chaudhary, Ankush ; Parihar, Narendra ; Rao, Rakesh ; Motzny, Steve ; Moroz, Victor ; Mahapatra, Souvik (2017) Predictive TCAD for NBTI stress-recovery in various device architectures and channel materials In: 2017 IEEE International Conference on Reliability Physics Symposium (IRPS), 2-6 April 2017, Monterey, CA, USA.

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A 3-D TCAD framework is proposed for simulating Negative Bias Temperature Instability (NBTI) in Silicon (Si) and Silicon Germanium (SiGe) channel p-MOSFETs. Different types of device architectures such as planar, bulk and SOI FinFETs as well as Gate All Around Nanowire FETs (GAA NWFETs) have been simulated. The framework can predict device degradation during stress and the recovery of degradation after stress. NBTI measured data are predicted for Si and SiGe planar devices with different Ge% and Si FinFETs. Calibrated TCAD is used to predict impact of technology scaling on NBTI, for constant gate bias (VG) and constant overdrive (VOV) stress. It is reported that (1) reducing the fin and NW width makes NBTI reliability worse for FinFETs and NWFETs, (2) devices with SiGe channel offer superior NBTI reliability as compared to Si channel, consistent with published reports, and (3) GAA NWFETs are more NBTI-prone when compared to planar and FinFET architectures. The fin and NW geometry dependence of NBTI Voltage Acceleration Factor (VAF) and degradation at End-Of-Life (EOL) have been investigated in detail.

Item Type:Conference or Workshop Item (Paper)
Source:Copyright of this article belongs to Institute of Electrical and Electronics Engineers.
Keywords:TCAD; NBTI; Si Channel; SiGe Channel; Finfet; GAA NWFET; Interface Trap Generation; Hole Trapping; End of Life (EOL) Degradation; Voltage Acceleration Factor (VAF)
ID Code:112558
Deposited On:09 Apr 2018 11:26
Last Modified:09 Apr 2018 11:26

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