A framework for estimating peak power in gate-level circuits

Chakraborty, Diganchal ; Chakrabarti, P. P. ; Mondal, Arijit ; Dasgupta, Pallab (2006) A framework for estimating peak power in gate-level circuits In: 16th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2006, 13-15 September 2006, Montpellier, France.

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Official URL: http://link.springer.com/chapter/10.1007%2F1184708...

Related URL: http://dx.doi.org/10.1007/11847083_56


This paper presents a framework for estimation of peak power dissipation in gate level circuits. This measure can be used to make architectural or design style decisions during the VLSI synthesis process. The proposed method first builds a symbolic event list for every possible input and uses this as the database for computing the peak power estimate. A novel heuristic search based method is presented which works on this symbolic event list to estimate peak power. Experimental results on ISCAS’89 benchmarks demonstrate the proposed method to be effective on moderately large circuits.

Item Type:Conference or Workshop Item (Paper)
Source:Copyright of this article belongs to Springer-Verlag Berlin Heidelberg.
ID Code:102332
Deposited On:09 Mar 2018 10:15
Last Modified:09 Mar 2018 10:15

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