Operator scheduling revisited: a multi-objective perspective for fine-grained DVS architecture

Abstract

Functional units supporting dynamic voltage and frequency scaling are being used today for fine grained power managed digital integrated circuits. The stringent power budget of these low power circuits have driven chip designers to optimize power at the cost of area and delay, which were the traditional cost criteria for circuit optimization. The emerging scenario motivates us to revisit the classical operator scheduling problem under the availability of DVFS enabled functional units that can trade-off cycles with power. We study the design space defined due to this trade-off and present a branch-and-bound(B/B) algorithm to explore this state space and report the pareto-optimal front with respect to area and power. Experimental results show that the algorithm that operates without any user constraint is able to solve the problem for most available benchmarks, and the use of power budget or area budget constraints leads to significant performance gain.