Interactive test-bench synthesis for assertion-based verification

Banerjee, A. ; Chakravorty, S. ; Pal, B. ; Dasgupta, P. (2005) Interactive test-bench synthesis for assertion-based verification In: 2005 Annual IEEE India Conference - Indicon, 11-13 December 2005.

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In recent years, Assertion-Based Verification (ABV) is being widely accepted as a key technology in the pre-silicon validation of chips. Developing test sequences that trigger non-vacuous interpretations of the assertions is a complex problem, and is considered to be one of the major challenges in ABV. In this paper we present a language called Open-LTL for specifying temporal specifications and input constraints in a unified way and a formal methodology for generating interactive test-benches from these specifications that drive protocol compliant inputs to the Design-Under-Test (DUT).

Item Type:Conference or Workshop Item (Paper)
Source:Copyright of this article belongs to Institute of Electrical and Electronics Engineers.
ID Code:101696
Deposited On:09 Mar 2018 10:18
Last Modified:09 Mar 2018 10:18

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