Synthesis of system verilog assertions

Das, S. ; Mohanty, R. ; Dasgupta, P. ; Chakrabarti, P. P. (2006) Synthesis of system verilog assertions In: Design, Automation and Test in Europe, 2006 - DATE '06, 6-10 March 2006, Munich, Germany.

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In recent years, assertion-based verification is being widely accepted as a key technology in the pre-silicon validation of system-on-chip (SOC) designs. The System Verilog language integrates the specification of assertions with the hardware description. In this paper we show that there are several compelling reasons for synthesizing assertions in hardware, and present an approach for synthesizing System Verilog assertions (SVA) in hardware. Our method investigates the structure of SVA properties and decomposes them into simple communicating parallel hardware units that together act as a monitor for the property. We present a tool that performs this synthesis, and also show that the chip area required by the monitors for a industry standard ABV IP for the ARMAMBA AHB protocol is quite modest.

Item Type:Conference or Workshop Item (Paper)
Source:Copyright of this article belongs to Institute of Electrical and Electronics Engineers.
ID Code:101688
Deposited On:09 Mar 2018 10:18
Last Modified:09 Mar 2018 10:18

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