Bounded delay timing analysis using boolean satisfiability

Roy, Suchismita ; Chakrabarti, P. P. ; Dasgupta, Pallab (2007) Bounded delay timing analysis using boolean satisfiability In: 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 6-10 January 2007.

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This paper proposes an accurate technique for computing critical delay of a circuit under a bounded delay model. The bounded delay model is better adapted to capture real time variations in the gate delays due to changes in operating conditions. But this flexibility comes at a price, since the uncertainty in gate delays increases the complexity of the timing analysis problem greatly. But we have shown in this paper that using fixed delay timing analysis with worst case delay values for gates can potentially underestimate the critical delay of a circuit. We propose a SAT based methodology for timing analysis in a bounded delay framework which utilises the phenomenal speed and efficiency of modern SAT solvers, and report encouraging results on the ISCAS benchmark circuits.

Item Type:Conference or Workshop Item (Paper)
Source:Copyright of this article belongs to Institute of Electrical and Electronics Engineers.
ID Code:101677
Deposited On:09 Mar 2018 10:17
Last Modified:09 Mar 2018 10:17

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