Inline assertions - embedding formal properties in a test bench

Hazra, Aritra ; Ghosh, Priyankar ; Dasgupta, Pallab ; Chakrabarti, Partha Pratim (2009) Inline assertions - embedding formal properties in a test bench In: 2009 22nd International Conference on VLSI Design, 5-9 January 2009, New Delhi, India.

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The scope of immediate assertions in SystemVerilog is restricted to Boolean properties, where as temporal properties are specified as concurrent assertions. Concurrent assertion statements can also be embedded in a procedural block - known as procedural concurrent assertions which are used under restricted situations. This paper introduces the notion of inline assertions which generalizes the embedding of temporal properties within the procedural code of a test bench. The paper proposes verification methodologies for inline assertions and compares them with the traditional approaches of formal property verification and dynamic assertion based verification. The paper also focuses on coverage related issues when the intent of a concurrent assertion is modeled as an inline assertion.

Item Type:Conference or Workshop Item (Paper)
Source:Copyright of this article belongs to Institute of Electrical and Electronics Engineers.
Keywords:Delay; System Testing; Master-Slave; Protocols; Very Large Scale Integration; Computer Science; Design Engineering; Monitoring; Context Modeling
ID Code:101667
Deposited On:12 Dec 2016 10:00
Last Modified:12 Dec 2016 10:00

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