Coverage management with inline assertions and formal test points

Hazra, Aritra ; Ghosh, Priyankar ; Dasgupta, Pallab ; Chakrabarti, Partha Pratim (2010) Coverage management with inline assertions and formal test points In: 2010 23rd International Conference on VLSI Design, 3-7 January 2010, Bangalore, India.

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This paper studies the problem of coverage management with two emerging formalisms in simulation based validation, namely formal specification of test points and the use of inline temporal assertions. We present methods for checking whether a test-bench with inline assertion covers a set of formal test points. This is particularly useful in developing verification IPs for standard on-chip protocols where the development team must make sure that the test bench provided in the verification IP checks all the important aspects of the protocol. We demonstrate the efficacy of our approach over the ARM AMBA verification IP.

Item Type:Conference or Workshop Item (Paper)
Source:Copyright of this article belongs to Institute of Electrical and Electronics Engineers.
Keywords:Industrial Property; Formal Specification; Formal Verification
ID Code:101661
Deposited On:12 Dec 2016 10:07
Last Modified:12 Dec 2016 10:07

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