Accelerating synchronous sequential circuits using an adaptive clock

Mondal, Arijit ; Chakrabarti, Partha ; Dasgupta, Pallab (2010) Accelerating synchronous sequential circuits using an adaptive clock In: 2010 23rd International Conference on VLSI Design, 3-7 January 2010, Bangalore, India.

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In this paper we propose a scheme for enhancing the timing performance of a pre-designed synchronous sequential circuit. In the proposed scheme, a circuit is driven by two clocks. One of them is the conventional clock while the other one, having a shorter period, is applied when the circuit stabilizes well before the critical delay. We use a symbolic algorithm to analyze the timing behavior of the synchronous sequential circuit and provide add-on circuitry to select the appropriate clock based on the current state of the circuit. We demonstrate an appreciable gain (67% in average) in timing performance on several benchmark circuits.

Item Type:Conference or Workshop Item (Paper)
Source:Copyright of this article belongs to Institute of Electrical and Electronics Engineers.
Keywords:VLSI; CAD; Timing Optimization; Delays; Sequential Circuits; Timing
ID Code:101659
Deposited On:12 Dec 2016 10:09
Last Modified:12 Dec 2016 10:09

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