Multi-objective low-power CDFG scheduling using fine-grained DVS architecture in distributed framework

Mukherjee, R. ; Ghosh, P. ; Sravan Kumar, N. ; Dasgupta, P. ; Pal, A. (2012) Multi-objective low-power CDFG scheduling using fine-grained DVS architecture in distributed framework In: 2012 International Symposium on Electronic System Design (ISED), 19-22 December 2012, Kolkata, India.

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Official URL: http://ieeexplore.ieee.org/document/6526598/

Related URL: http://dx.doi.org/10.1109/ISED.2012.51

Abstract

There has been a renewed interest in the operator scheduling problem due to the down-scaling trend of CMOS technology and the increasing adoption of the fine-grained power management at the level of individual functional unit. Traditionally branch-and-bound has been a popular choice for determining the pareto-optimal frontier with respect to area and power under certain user constraints. In this paper we explore the scope of parallelism within the branch-and-bound(B/B) algorithm for control and data-flow intensive circuits in order to address the scalability issue. The scheduling also aims at maximum conditional and unconditional resource sharing and is able to attain sufficient area and power gains for complex benchmarks under strict and relaxed timing constraints. Experimental results reveals that the distributed framework is able to parallelize the search space uniformly and is able to achieve promising speedup compared to the serial B/B counterpart.

Item Type:Conference or Workshop Item (Paper)
Source:Copyright of this article belongs to Institute of Electrical and Electronics Engineers.
Keywords:Scheduling; Cmos Integrated Circuits; Data Flow Analysis; Pareto Analysis
ID Code:101625
Deposited On:12 Dec 2016 11:02
Last Modified:12 Dec 2016 11:02

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