A library for passive online verification of analog and mixed-signal circuits

Pal, Debjit ; Dasgupta, Pallab ; Mukhopadhyay, Siddhartha (2012) A library for passive online verification of analog and mixed-signal circuits In: 2012 25th International Conference on VLSI Design (VLSID), 7-11 January 2012, Hyderabad, India.

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Official URL: http://ieeexplore.ieee.org/document/6167779/

Related URL: http://dx.doi.org/10.1109/VLSID.2012.98


The development and use of assertions in the Analog and Mixed-signal (AMS) domain is a subject which has attracted significant attention lately from the verification community. Recent studies have suggested that natural extensions of assertion languages (like PSL and SVA) into the AMS domain are not expressive enough to capture many AMS behaviors, and that a library of auxiliary AMS functions are needed along with the assertion language. The integration of auxiliary functions with the core fabric of a temporal logic is non-trivial and can be challenging for a verification engineer. In this paper we propose a purely library-based verification approach, where libraries for checking elementary properties can be naturally connected with libraries for auxiliary functions to monitor complex AMS behaviors. We study the modeling of behaviors with the proposed library, and outline the main challenges and their solutions towards implementing the verification library over commercial AMS simulators.

Item Type:Conference or Workshop Item (Paper)
Source:Copyright of this article belongs to Institute of Electrical and Electronics Engineers.
Keywords:Libraries; Phase Locked Loops; Monitoring; Delay; Regulators; Steady-State; Hardware Design Languages
ID Code:101619
Deposited On:12 Dec 2016 11:04
Last Modified:12 Dec 2016 11:04

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