Hardware accelerated constrained random test generation

Pal, B. ; Sinha, A. ; Dasgupta, P. ; Chakrabarti, P. P. ; De, K. (2007) Hardware accelerated constrained random test generation IET Computers & Digital Techniques, 1 (4). p. 423. ISSN 1751-8601

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Official URL: http://ieeexplore.ieee.org/document/4271387/

Related URL: http://dx.doi.org/10.1049/iet-cdt:20070016


Recent design and verification languages, such as SystemVerilog, support a rich test bench language, which provides significant support towards developing layered, structured, constrained random test bench architectures. Typically, the test bench language offers many features that are not synthesisable and therefore cannot be carried into the hardware for hardware accelerated simulation. One of the main challenges in improving the performance of hardware accelerated simulation is to run the task of random value selection under specified constraints in hardware. This problem (possibly for the first time) is addressed and a two-step approach is presented. In the first step, the constraints are pre-processed in software to generate a set of entailed regions. In the second step, random value selection is performed in hardware using the entailed regions pre-computed in the first step. It is shown that this method has modest area overhead and produces constraint satisfying random valuations within very few cycles. Results on test bench architectures for the ARM AMBA Bus and IBM CoreConnect protocol suites have been reported.

Item Type:Article
Source:Copyright of this article belongs to Institution of Engineering and Technology.
Keywords:Logic Testing; Hardware Description Languages; Logic CAD
ID Code:101438
Deposited On:12 Dec 2016 11:33
Last Modified:12 Dec 2016 11:33

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