Event propagation for accurate circuit delay calculation using SAT

Roy, Suchismita ; Chakrabarti, P. P. ; Dasgupta, Pallab (2007) Event propagation for accurate circuit delay calculation using SAT ACM Transactions on Design Automation of Electronic Systems, 12 (3). Article ID 36. ISSN 1084-4309

Full text not available from this repository.

Official URL: http://dl.acm.org/citation.cfm?id=1255473

Related URL: http://dx.doi.org/10.1145/1255456.1255473


A SAT-based modeling for event propagation in gate-level digital circuits, which is used for accurate calculation of critical delay in combinational and sequential circuits, is presented in this article. The accuracy of the critical delay estimation process depends on the accuracy with which the circuit in operation is modeled. A high level of precision in the modeling of the internal events in a circuit for the sake of greater accuracy causes a combinatorial blowup in the size of the problem, resulting in a scalability bottleneck for which most existing techniques effect a trade-off by restricting themselves to less precise models. SAT based techniques have a good track record in efficiency and scalability when the problem sizes become too large for most other methods. This article proposes a SAT-based technique for symbolic event propagation within a circuit which facilitates the estimation of the critical delay of circuits with a greater degree of accuracy, while at the same time scaling efficiently to large circuits. We report very encouraging results on the ISCAS85 and ISCAS89 benchmark circuits using the proposed technique.

Item Type:Article
Source:Copyright of this article belongs to Association for Computing Machinery.
ID Code:101436
Deposited On:12 Dec 2016 11:35
Last Modified:12 Dec 2016 11:37

Repository Staff Only: item control page