Synchronizing AMS Assertions with AMS Simulation: from theory to practice

Mukherjee, Subhankar ; Dasgupta, Pallab ; Mukhopadhyay, Siddhartha ; Little, Scott ; Havlicek, John ; Chandrasekaran, Srikanth (2012) Synchronizing AMS Assertions with AMS Simulation: from theory to practice ACM Transactions on Design Automation of Electronic Systems, 17 (4). pp. 1-25. ISSN 1084-4309

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The verification community anticipates the adoption of assertions in the Analog and Mixed-Signal (AMS) domain in the near future. Several questions need to be answered before AMS assertions are brought into practice, such as: (a) How will the languages for AMS assertions be different from the ones in the digital domain? (b) Does the analog simulator have to be assertion aware? (c) If so, then how and where on the time line will the AMS assertion checker synchronize with the analog simulator? and (d) What will be the performance penalty for monitoring AMS assertions accurately over analog simulation? This article attempts to answer these questions through theoretical analysis and empirical results obtained from industrial test cases. We study logics which extend Linear Temporal Logic (LTL) with predicates over real variables, and show that further extensions allowing the binding of real-valued variables across time makes the logic undecidable. We present a toolkit which can integrate with existing AMS simulators for checking AMS assertions on practical designs. We study the problem of synchronizing the AMS simulator with the AMS assertion checker and demonstrate the performance penalty of different synchronization options.

Item Type:Article
Source:Copyright of this article belongs to Association for Computing Machinery.
ID Code:101328
Deposited On:12 Dec 2016 11:07
Last Modified:12 Dec 2016 11:07

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