Sub-20 nm gate length FinFET design: can high-k spacers make a difference?

Abstract

Sub-20 nm gate length FinFETs, are constrained by the very thin fin thickness (T_FIN) necessary to maintain acceptable short-channel performance. For the 45 nm technology node and below, a novel device design methodology for undoped underlapped FinFETs with high-kappa spacers is presented to achieve higher circuit speed and SRAM cells with higher stability, lower leakage, faster access times and higher robustness to process variations compared to overlapped FinFETs. While comparing different FinFETs, we propose ON-current per fin as the parameter to be optimized instead of ON-current normalized to electrical width.