Impact of substrate bias on p-MOSFET negative bias temperature instability

Abstract

The Negative Bias Temperature Instability (NBTI) of p-MOSFETs is an important reliability issue for digital as well as analog CMOS circuits. To date, characterization and modeling efforts to analyze the NBTI mechanism involve devices stressed with zero substrate bias (V_B). However, many circuits utilize nonzero V_B to vary the device threshold voltage (V_T), (e.g., for dual V_TCMOS, standby leakage reduction, etc.). This paper aims to systematically study NBTI for V_B0 V stress, which, to the best of our knowledge, has not been done so far. It is shown that NBTI increases for V_B0 V stress. This is attributed to enhanced interface (N_IT) and bulk (N_OT) trap generation due to impact ionization and hot-hole (HH) generation. The role of gate bias (V_G), V_B, Temperature (T) and oxide thickness (T_PHY) is studied. This work would help all efforts in determining: (i) reliability budget for any operating V_B; (ii) proper choice of stress V_B during accelerated aging tests; and (iii) suitable TCAD and SPICE models.