Impact of substrate bias on p-MOSFET negative bias temperature instability

Kurnars, P. B. ; Dalei, T. R. ; Varghese, D. ; Saba, D. ; Mahapatra, S. ; Alam, M. A. (2005) Impact of substrate bias on p-MOSFET negative bias temperature instability In: Proceedings of 2005 43rd Annual IEEE International Reliability Physics Symposium., 17-21 April, 2005, San Jose, CA, USA.

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The Negative Bias Temperature Instability (NBTI) of p-MOSFETs is an important reliability issue for digital as well as analog CMOS circuits. To date, characterization and modeling efforts to analyze the NBTI mechanism involve devices stressed with zero substrate bias (VB). However, many circuits utilize nonzero VB to vary the device threshold voltage (VT), (e.g., for dual VTCMOS, standby leakage reduction, etc.). This paper aims to systematically study NBTI for VB0 V stress, which, to the best of our knowledge, has not been done so far. It is shown that NBTI increases for VB0 V stress. This is attributed to enhanced interface (NIT) and bulk (NOT) trap generation due to impact ionization and hot-hole (HH) generation. The role of gate bias (VG), VB, Temperature (T) and oxide thickness (TPHY) is studied. This work would help all efforts in determining: (i) reliability budget for any operating VB; (ii) proper choice of stress VB during accelerated aging tests; and (iii) suitable TCAD and SPICE models.

Item Type:Conference or Workshop Item (Paper)
Source:Copyright of this article belongs to Institute of Electrical and Electronics Engineers.
ID Code:112610
Deposited On:12 Apr 2018 07:22
Last Modified:12 Apr 2018 07:22

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