Items where Author is "Baghini, M. S."

Article

Gilda, N. A. ; Nag, S. ; Patil, S. ; Baghini, M. S. ; Sharma, D. K. ; Rao, V. R. (2011) Current excitation method for ΔR measurement in piezo-resistive sensors with a 0.3-ppm resolution Transactions on Instrumentation and Measurement, PP (99). pp. 1-8. ISSN 0018-9456

Shrivastava, M. ; Mehta, R. ; Gupta, S. ; Agarwal, N. ; Baghini, M. S. ; Sharma, D. K. ; Schulz, T. ; Armin, K. ; Molzer, W. ; Gossner, H. ; Rao, V. R. (2011) Toward system on chip (SoC) development using FinFET technology: challenges, solutions, process co-development & optimization guidelines IEEE Transactions on Electron Devices, 58 (6). pp. 1597-1607. ISSN 0018-9383

shrivatsava, M. ; Jain, R. ; Baghini, M. S. ; Gossner, H. ; Rao, V. R. (2010) A solution toward the OFF-state degradation in drain-extended MOS device IEEE Transactions on Electron Devices, 57 (12). pp. 3536-3539. ISSN 0018-9383

Shrivastava, M. ; Gossner, H. ; Baghini, M. S. ; Rao, V. R. (2010) 3D TCAD base d approach for the evaluation of nanoscale devices during ESD failure 7th International SoC Design Conference (ISOCC 2010) . pp. 268-271.

Sachid, A. B. ; Baghini, M. S. ; Sharma, D. K. ; Rao, V. R. (2010) Alternate scaling strategies for Multi-Gate FETs for high-performance and low-power applications 7th International SoC Design Conference (ISOCC 2010) . pp. 256-259.

Shrivastava, M. ; Gossner, H. ; Baghini, M. S. ; Rao, V. R. (2010) On the Transient behavior of various drain extended MOS devices under the ESD stress condition 7th International SoC Design Conference (ISOCC 2010) . pp. 264-267.

Shrivastava, M. ; Gossner, H. ; Baghini, M. S. ; Rao, V. R. (2010) Part I: On the behavior of STI-type DeNMOS device under ESD conditions IEEE Transactions on Electron Devices, 57 (9). pp. 2235-2242. ISSN 0018-9383

Shrivastava, M. ; Gossner, H. ; Baghini, M. S. ; Rao, V. R. (2010) Part II: On the three-dimensional filamentation and failure modeling of STI type DeNMOS device under various ESD conditions IEEE Transactions on Electron Devices, 57 (9). pp. 2243-2250. ISSN 0018-9383

Shrivastava, M. ; Baghini, M. S. ; Sharma, D. K. ; Rao, V. R. (2010) A novel bottom spacer FinFET structure for improved short-channel, power-delay, and thermal performance IEEE Transactions on Electron Devices, 57 (6). pp. 1287-1294. ISSN 0018-9383

Shrivastava, M. ; Schneider, J. ; Baghini, M. S. ; Gossner, H. ; Rao, V. R. (2010) On the failure mechanism and current instabilities in RESURF type DeNMOS device under ESD conditions Proceedings of the 2010 IEEE International Reliability Physics Symposium (IRPS) . pp. 841-845. ISSN 1541-7026

Sachid, A. B. ; Thakker, R. A. ; Sathe, C. ; Baghini, M. S. ; Sharma, D. K. ; Ramgopal Rao, V. ; Patil, M. B. (2010) Auto-BET-AMS: an automated device and circuit optimization platform to benchmark emerging technologies for performance and variability using an analog and mixed-signal design framework Proceedings of the 11th International Symposium on Quality Electronic Design (ISQED 2010) . pp. 713-720. ISSN 1948-3287

Shrivastava, M. ; Baghini, M. S. ; Gossner, H. ; Rao, V. R. (2010) Part I. Mixed-signal performance of various high-voltage drain-extended MOS devices IEEE Transactions on Electron Devices, 57 (2). pp. 448-457. ISSN 0018-9383

Shrivastava, M. ; Baghini, M. S. ; Gossner, H. ; Rao, V. R. (2010) Part I: Mixed-signal performance of various high-voltage drain-extended MOS devices IEEE Transactions on Electron Devices, 57 (2). pp. 448-457. ISSN 0018-9383

Shrivastava, M. ; Baghini, M. S. ; Gossner, H. ; Rao, V. R. (2010) Part II. A novel scheme to optimize the mixed-signal performance and hot-carrier reliability of drain-extended MOS devices IEEE Transactions on Electron Devices, 57 (2). pp. 458-465. ISSN 0018-9383

Shrivastava, M. ; Baghini, M. S. ; Gossner, H. ; Rao, V. R. (2010) Part II: A novel scheme to optimize the mixed-signal performance and hot-carrier reliability of drain-extended MOS devices IEEE Transactions on Electron Devices, 57 (2). pp. 458-465. ISSN 0018-9383

Shrivastava, M. ; Verma, B. ; Baghini, M. S. ; Russ, C. ; Sharma, D. K. ; Gossner, H. ; Rao, V. R. (2009) Benchmarking the device performance at sub 22 nm node technologies using an SoC framework Proceedings of the International Electron Devices Meeting (IEDM) . pp. 1-4.

Shrivastava, M. ; Bychikhin, S. ; Pogany, D. ; Schneider, J. ; Baghini, M. S. ; Gossner, H. ; Gornik, E. ; Rao, V. R. (2009) Filament study of STI type drain extended NMOS device using transient interferometric mapping Proceedings of the International Electron Devices Meeting (IEDM) . pp. 1-4.

Shrivastava, M. ; Schneider, J. ; Jain, R. ; Baghini, M. S. ; Gossner, H. ; Ramgopal Rao, V. (2009) IGBT plugged in SCR device for ESD protection in advanced CMOS technology 31st IEEE Annual InternationaEOS/ESD Symposium, Anaheim, CA, USA . pp. 1-9.

Navan, R. R. ; Thakker, R. A. ; Tiwari, S. P. ; Baghini, M. S. ; Patil, M. B. ; Mhaisalkar, S. G. ; Rao, V. R. (2009) DC & transient circuit simulation methodologies for organic electronics Proceedings of the IEEE International Workshop on Electron Devices & Semiconductor Technology, Mumbai, India . pp. 1-4.

Sachid, A. B. ; Kulkarni, G. S. ; Baghini, M. S. ; Sharma, D. K. ; Rao, V. R. (2009) Highly robust nanoscale planar double-gate MOSFET device and SRAM cell immune to gate-misalignment and process variations Proceedings of the IEEE International Workshop on Electron Devices & Semiconductor Technology, Mumbai, India . pp. 1-4.

Shrivastava, M. ; Schneider, J. ; Baghini, M. S. ; Gossner, H. ; Rao, V. R. (2009) Highly resistive body STI NDeMOS: an optimized DeMOS device to achieve moving current filaments for robust ESD protection Proceedings of the 2009 IEEE International Reliability Physics Symposium (IRPS) . pp. 754-759. ISSN 1541-7026

Shrivastava, M. ; Schneider, J. ; Baghini, M. S. ; Gossner, H. ; Rao, V. R. (2009) A new physical insight and 3D device modeling of STI type denmos device failure under ESD conditions Proceedings of the 2009 IEEE International Reliability Physics Symposium (IRPS) . pp. 669-675. ISSN 1541-7026

Thakker, R. A. ; Sathe, C. ; Sachid, A. B. ; Baghini, M. S. ; Rao, V. R. ; Patil, M. B. (2009) Automated design and optimization of circuits in emerging technologies Proceedings of the 14th Asiaand South Pacific Design Automation Conference" (ASP-DAC 2009), Yokohama, Japan . pp. 504-509.

Sachid, A. B. ; Francis, R. ; Baghini, M. S. ; Sharma, D. K. ; Bach, K. -H. ; Mahnkopf, R. ; Rao, V. R. (2008) Sub-20 nm gate length FinFET design: can high-k spacers make a difference? Proceedings of the International Electron Devices Meeting (IEDM) . pp. 1-4.

Shrivastava, M. ; Baghini, M. S. ; Sachid, A. B. ; Sharma, D. K. ; Rao, V. R. (2008) A novel and robust approach for common mode feedback using IDDG FinFET IEEE Transactions on Electron Devices, 55 (11). pp. 3274-3282. ISSN 0018-9383