Jha, Neeraj K. ; Ramgopal Rao, V. ; Woo, J. C. S. (2002) Optimization of single halo p-MOSFET implant parameters for improved analog performance and reliability Proceedings of the 32nd European Solid-State Device Research Conference (ESSDERC), Florence, Italy . pp. 603-606.
![]()
|
PDF
- Publisher Version
104kB |
Official URL: http://dspace.library.iitb.ac.in/xmlui/bitstream/h...
Abstract
The effect of Channel Hot Carrier (CHC) stress under typical analog operating conditions is studied for p-MOSFETs. Our detailed characterization results show that Single Halo devices not only show improved performance, but also are immune to CHC degradation under various operating conditions.
Item Type: | Article |
---|---|
Source: | Copyright of this article belongs to Proceedings of the 32nd European Solid-State Device Research Conference (ESSDERC), Florence, Italy. |
ID Code: | 80937 |
Deposited On: | 02 Feb 2012 14:27 |
Last Modified: | 18 May 2016 22:41 |
Repository Staff Only: item control page