Vairagar, A. V. ; Patil, S. B. ; Pete, D. J. ; Waghmare, P. C. ; Dusane, R. O. ; Venkatraman, N. ; Ramgopal Rao, V. (2002) Suppression of boron penetration by hot wire CVD polysilicon Proceedings of the 9th IEEE International Symposium on Physical and Failure Analysis of Integrated Circuits, Singapore . pp. 223-226.
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Official URL: http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumb...
Related URL: http://dx.doi.org/10.1109/IPFA.2002.1025667
Abstract
In the current and future deep sub-micron technologies, boron penetration through the gate dielectric is a severe reliability concern for the dual gate CMOS technology. In this paper we report results of our attempts to exploit the potential of Hot Wire CVD (HWCVD) for depositing poly-Si gate for CMOS technology. The effect of grain size of poly-Si gate on boron penetration is studied by varying the poly-Si grain size through variation in the HWCVD parameters.
| Item Type: | Article |
|---|---|
| Source: | Copyright of this article belongs to Proceedings of the 9th IEEE International Symposium on Physical and Failure Analysis of Integrated Circuits, Singapore. |
| ID Code: | 79778 |
| Deposited On: | 28 Jan 2012 11:48 |
| Last Modified: | 28 Jan 2012 11:48 |
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