Kumar, D. V. ; Mohapatra, N. R. ; Patil, M. B. ; Rao, V. R. (2003) Application of look-up table approach to high-K gate dielectric MOS transistor circuits Proceedings - IEEE International Conference on VLSI Design . pp. 128-133. ISSN 1063-9667
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Official URL: http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumb...
Related URL: http://dx.doi.org/10.1109/ICVD.2003.1183126
Abstract
In this paper, we study the circuit performance issues of high-K gate dielectric MOSFETs using the Look-up Table (LUT) approach. The LUT approach is implemented in a public-domain circuit simulator SEQUEL. We observed an excellent match between LUT simulator and mixed mode simulations using MEDICI. This work clearly demonstrates the predictive power of the new simulator, as it enables evaluation of circuits directly from device simulation results without going through model parameter extraction.
| Item Type: | Article |
|---|---|
| Source: | Copyright of this article belongs to IEEE. |
| ID Code: | 79766 |
| Deposited On: | 28 Jan 2012 11:48 |
| Last Modified: | 28 Jan 2012 11:48 |
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