Sachid, A. B. ; Baghini, M. S. ; Sharma, D. K. ; Rao, V. R. (2010) Alternate scaling strategies for Multi-Gate FETs for high-performance and low-power applications 7th International SoC Design Conference (ISOCC 2010) . pp. 256-259.
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Official URL: http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arn...
Related URL: http://dx.doi.org/10.1109/SOCDC.2010.5682924
Abstract
This paper focuses on the alternate strategies to enable scaling of Multi-Gate FETs into sub-22 nm nodes. Scaling is not only limited by device level challenges like increasing parasitic resistances and capacitances, but also circuit level challenges like increasing interconnect parasitics, variability etc. The alternate scaling strategies consider both device level and circuit level challenges to obtain overall benefits with scaling.
| Item Type: | Article |
|---|---|
| Source: | Copyright of this article belongs to 7th International SoC Design Conference (ISOCC 2010). |
| ID Code: | 79732 |
| Deposited On: | 28 Jan 2012 11:58 |
| Last Modified: | 28 Jan 2012 11:58 |
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