Datta, Arnab ; Asnani, Rajesh ; Mahapatra, Souvik (2009) A novel gate-assisted reverse-read scheme to control bit coupling and read disturb for multibit/cell operation in deeply scaled split-gate SONOS flash EEPROM cells IEEE Electron Device Letters, 30 (8). pp. 885-887. ISSN 0741-3106
Full text not available from this repository.
Official URL: http://ieeexplore.ieee.org/document/5165097/
Related URL: http://dx.doi.org/10.1109/LED.2009.2025060
Abstract
A dual-node split-gate silicon-oxide-nitride-oxide-silicon cell with a novel read scheme is proposed for 2-bit/cell operation. Using suitable gate screening bias in reverse read, bit coupling can be reduced, even when low read VD is used to keep read disturb under control. The proposed read scheme maintains the memory window for dual-bit/cell operation for deeply scaled cells. Two-dimensional process, device, and Monte Carlo simulations are extensively used to design and understand cell operation.
| Item Type: | Article |
|---|---|
| Source: | Copyright of this article belongs to Institute of Electrical and Electronics Engineers. |
| Keywords: | 2-bit Operation; Bit Coupling; EEPROM; Gate Sensing; Nonvolatile Semiconductor Memory; Read Disturb; Scaling; Silicon–Oxide–Nitride–Oxide–Silicon (SONOS); Split Gate; Stack Gate |
| ID Code: | 112636 |
| Deposited On: | 02 Apr 2018 09:28 |
| Last Modified: | 02 Apr 2018 09:28 |
Repository Staff Only: item control page
